Improvement and Hardware Design of Image Denoising Algorithm Based on Deep Learning

Noise is always generated in the process of image generation and transmission, which hinders people from obtaining original image information, so image denoising has a wide range of applications. However, the image denoising algorithm based on deep learning has the disadvantages of large number of parameters and long inference time. Therefore, this paper proposes an improved lightweight neural network model in image denoising, compared with the DnCNN, saving up to 90.0% parameters in memory and increasing 21.4% inference speed. In addition, the cost and power consumption of commonly used neural network inference platforms (CPU, GPU) are relatively high, and it is difficult to deploy them in embedded devices. This paper completes the hardware implementation of the network structure through the Verilog hardware description language, and optimizes the resource occupation and circuit power consumption, and finally deploys the image denoising model on a FPGA. The experimental results show that the main frequency of the accelerator reaches 200 MHz, peak throughput is 200.207GOPS, and the energy consumption ratio is 17.183 GOPS/W, which is 1.9 times higher than the GPU and 26.2 times higher than the CPU.