Analysis and Design of Low-Noise Low-Offset Comparators for High-Performance ADC

The need for low-power high-resolution analog-to-digital converter (ADC) used in dynamic sensors is pushing towards the use of low-noise and low-offset dynamic comparators to improve power efficiency and speed. In this paper, we have compared state-of-the-art dynamic comparators which focus on low-noise and low-offset. They are designed in <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.18\mu \mathrm{m}$</tex> CMOS technology. StrongARM (SA) latch with embedded preamplifier achieves <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$120-\mu \mathrm{V}$</tex> input-referred noise while consuming only 1 pJ per comparison under 1.85-V supply. SA with Floating Inverter Amplifier (FIA) has lowest figure of merit (FOM) which represents the power efficiency of a comparator. Based on the simulation & analysis results, we demonstrate SA latch with embedded preamplifier and SA latch with FIA are good candidates for low-power high-resolution analog-to-digital converter (ADC).