A Low-Area High-Precision 100 MSPS 9-Bit Current-Steering DAC In 130nm BiCOMS

This paper proposes a 9-bit binary-coded current-Steering Digital-to-Analog Converter (DAC), which is designed using 130 nm SiGe BiCOMS process. The sampling rate is set to be 100 MSPS. Cadence Spectre is used to simulate static and dynamic error indicators to evaluate the performance of the DAC circuit. Simulation results show that the Differential Nonlinearity (DNL) is ±0.15 LSB and Integral Nonlinearity (INL) is ± 0.44 LSB, indicating high accuracy and excellent static performance. Additionally, the circuit has a low static power consumption of 3.6 mW. The Effective Number of Bits (ENOB) is maintained 8.74 at a sampling rate of 100 MSPS. The die area is only about <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.033 \text{mm}^{2}$</tex>.