A High-Stability and Fast-Transient Response LDO Design

In order to meet the requirements of portable electronic devices, a low-dropout linear regulator with a transient enhancement circuit is designed. A zero-pole tracking load current compensation circuit is utilized to eliminate the influence of the poles related to the output of the circuit and the loadrelated poles on the stability of the loop, ensuring that the circuit remains stable within the full load range. Considering the transient change of the output caused by sudden load changes, a transient enhancement circuit is designed to improve the load transient response by discharging the parasitic capacitance of the gate and the load capacitance of the power tube. The circuit is designed using the 0.18 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mu \mathbf{m}$</tex> CMOS process. The maximum output current of the circuit is 300 mA. Simulation results show that when the load current jumps from 1 mA to 300 mA within 1 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mu \mathbf{s}$</tex>, the underimpulse voltage is 37.6 mV, and the stabilization time is 1.5 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mu \mathbf{s}$</tex>. The upstroke voltage is 4.1 mV and the settling time is 3.5 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mu \mathbf{s}$</tex>.