Enhancing Reliability of NAND-based Memory String Through Efficient Fault Detection

Ensuring reliability of a memory structure is a most important aspect as memory chips play a vital role in any modern day SOC applications. With the increase in complexity of computations in mission critical systems, dependable memory structure becomes need of the hour. With the increase in memory density, rate of fault occurrence also goes exponential. Incorporating suitable fault detection and correction mechanisms across the string can enhance reliability. This paper focuses on designing a NAND based memory string starting with a basic floating gate memory cell model. The proposed work specifically targets the detection of ‘stuck-open' defects in the peripheral circuits, utilizing an electrical detection method that monitors current variations as an indicator of these faults. By independently monitoring the supply voltage across the array, the proposed approach aims to isolate and identify defects more effectively. The method is validated through HSPICE simulations, demonstrating its capability to reduce error rates significantly in comparison to conventional detection techniques, thereby improving the overall reliability of the NAND flash memory system.