An 18.6-to-27.6GHz High-Linear Wideband Low-Noise Amplifier Based on Gate-Source and Gate-Drain Magnetically Coupled Resonators

This paper proposes a high-linearity wideband low noise amplifier (LNA) for 18.6-to-27.6GHz mm-Wave communications. It features gate-source and gate-drain magnetically coupled resonators (MCRs) at the first and second stage, respectively, improving both bandwidth and noise figure (NF). The gate-source feedback MCR at the first stage together with shunt LC network achieve wideband input-impedance matching and optimize NF, while the gate-drain MCR and the capacitive feedback at the second stage neutralize the gate-drain parasitic capacitance and for voltage gain improvement. Besides, auxiliary transistor is employed to improve the small-signal linearity, i.e., the input third-order intercept point (IIP3). Implemented in 40nm CMOS technology, the proposed LNA achieves an input-impedance matching (S<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</inf>) <-8.7dB and power gain of 7.7-to-10.7dB when covering 18.6-to-27.6GHz. The IIP3 is >-3.1dBm and the minimum NF is 4dB. The LNA consumes 16.3mW from 1.1V power supply and occupies 0.11mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> active area.

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Published
2024-10-25
DOI
https://doi.org/10.1109/icicm63644.2024.10814398
Primary Topic
Radio Frequency Integrated Circuit Design
Type
article
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article

An 18.6-to-27.6GHz High-Linear Wideband Low-Noise Amplifier Based on Gate-Source and Gate-Drain Magnetically Coupled Resonators

Gengzhen Qi, Qi Wu
Radio Frequency Integrated Circuit Design
article

An 18.6-to-27.6GHz High-Linear Wideband Low-Noise Amplifier Based on Gate-Source and Gate-Drain Magnetically Coupled Resonators

Gengzhen Qi, Qi Wu
article en

Abstract

This paper proposes a high-linearity wideband low noise amplifier (LNA) for 18.6-to-27.6GHz mm-Wave communications. It features gate-source and gate-drain magnetically coupled resonators (MCRs) at the first and second stage, respectively, improving both bandwidth and noise figure (NF). The gate-source feedback MCR at the first stage together with shunt LC network achieve wideband input-impedance matching and optimize NF, while the gate-drain MCR and the capacitive feedback at the second stage neutralize the gate-drain parasitic capacitance and for voltage gain improvement. Besides, auxiliary transistor is employed to improve the small-signal linearity, i.e., the input third-order intercept point (IIP3). Implemented in 40nm CMOS technology, the proposed LNA achieves an input-impedance matching (S<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</inf>) <-8.7dB and power gain of 7.7-to-10.7dB when covering 18.6-to-27.6GHz. The IIP3 is >-3.1dBm and the minimum NF is 4dB. The LNA consumes 16.3mW from 1.1V power supply and occupies 0.11mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> active area.

Sun Yat-sen University (CN)
Affordable and clean energy
Openalex Percentile: Top 77%
Radio Frequency Integrated Circuit Design
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