Dynamic Path-Sensitive Memory Dependence Prediction

Memory dependence prediction is essential in superscalar out-of-order processors as it improves instruction-level parallelism efficiency by predicting dependencies between memory access instructions. However, existing state-of-the-art memory dependence predictors lack the ability to effectively utilize the dynamic execution information of conflicting instructions, leading to an excessive number of false positives and subsequently hindering overall performance. This work proposes Dynamic Path-Sensitive Memory Dependence Prediction (DPMDP), a novel dynamic path-sensitive memory dependence prediction method that dynamically selects the history length for each conflicting load instruction when multiple paths exist. Our key observation is that for load-store pairs with an initial occurrence of a violation if the conflicting store is waiting for an address translation that causes an execution delay, it does not create a dependency in the predictor initially and only creates it upon subsequent occurrences effectively. This observation is proven by running the SPEC CPU 2006 suite on the clock-accurate simulator GEM5. Through cycle-accurate simulation of the SPEC CPU 2006 suite, we show that DPMDP achieved an average performance improvement of 1.08% compared to Store Set and 13.06% compared to PHAST.