A Reference-Frequency Doubler with Integrated Duty-Cycle Corrector

This paper presents a reference-frequency doubler integrated with a duty cycle corrector. A mixed-signal structure is used in the duty cycle corrector. The digital logic control module controls the entire duty cycle calibration process to calibrate the duty cycle of the input reference signal to 50%. The proposed duty cycle corrector uses adjustable delay cells, introducing long and short delays for coarse and fine delay adjustments, respectively. It realizes a comprehensive performance in both correction accuracy and correction cycles. And the use of 4 identical adjustable delay cells helps generate the double-frequency signal through an XOR gate. The output doubled signal also has a duty cycle of about 50% in contrast to the conventional frequency doubler that uses separate DCC and XOR, where the duty-cycle of the output doubled signal is too small. This design is implemented in 40nm CMOS process and successfully achieves the capability to regulate the duty cycle of the input signal from 50%±20% to 50%±1.5% within an input frequency range of 40MHz to 70MHz, requiring only 40 to 80 clock cycles for calibration, thus generating a doubled frequency signal. The design is well-suited for application in PLL systems and significantly aids in reducing the output phase noise of the PLL.