A High Linearity Current-Mirror MAC Circuit Design for SRAM Computing-in-Memory

Computing-in-memory (CIM), as an emerging computer architecture, can reduce the power consumption and delays of data-intensive applications caused by frequent data migration. In traditional CIM architectures, high-precision convolutional computation is often performed with large computational non-linearities due to multi-bit weighting, which reduces the computational accuracy and energy efficiency of the system. This paper proposes a high linearity current-mirror MAC circuit (CMMC) and constructs a CIM architecture that can realize 8-bit MAC using a novel 8T SRAM, which adopts the current domain computation mode and has a higher computational linearity than that of the bit-line discharge mode in the charge domain. Under the 110nm process with a 1.2V supply voltage, the functional correctness of the circuit was verified through simulation, and its linearity was calculated to be up to 99.82%, significantly enhancing the accuracy of multi-bit convolutional computation. Furthermore, the storage for a single convolutional kernel in this design is unfolded in the row direction, endowing this CIM circuit architecture with excellent parallelism and scalability.