A Low Power Low Noise High Speed Comparator for Asynchronous SAR ADC

This paper presents a high speed, low power and low noise comparator for asynchronous SAR ADC use. In the proposed comparator, several techniques are used to improve the performance. The input pair of preamplifier are directly connected to the latch to improve the speed, and the stacked clocked tail technique is proposed to cut off the leakage path to save power, simultaneously enhancing the input transistors' gm/Id, thereby reducing the input referred noise. To alleviate the load of output nodes and enhance speed, an additional latch is added to isolate the large parasitic capacitance of the input transistors from comparator output. The post layout simulation result shows that in 28nm CMOS technology, with supply of 1V, the proposed comparator consumes only 45.73fJ energy per comparison with 10G clock. The input referred noise of comparator is 0.75mVrms and CLK-Q delay is 29.79ps. The FOM value is very competitive compared to the comparators presented latest.