Research on Storage Network Architecture Simulator for Group Convolution Feature Communication

In group convolution, feature communication exhibits complex behaviors, leading to memory access becoming one of the factors limiting performance. For this issue, our team has proposed an on-chip storage network with adaptive bandwidth for centralized distributed storage. To verify the effectiveness of the storage network architecture and achieve rapid iteration towards the optimal architecture, this paper constructs behavioral models for group convolution computation units and storage networks based on SystemC and TLM, enabling rapid adjustment of the architecture and its models through parameters. Firstly, by analyzing the computational behavior of group convolution, we abstracted the basic behavioral model of the computation unit. Through this foundational model, complex computational behavior models for group convolution feature communication can be constructed. Secondly, we constructed models for the structures within the storage network, including routers, nodes, storage units, and bus bridges. Furthermore, an AXI interconnect model was built to facilitate data transfer between the memory access behavior model of group convolution and the storage network model. Through the storage network architecture simulator, read and write frequencies of network buses and nodes, as well as the storage utilization rates of each accessed network node, can be obtained to evaluate the performance of current architectural parameters and make appropriate adjustments to the architecture. The validity of the simulator in this paper was effectively verified through the simulation of 3×3 group convolution computation and a storage network architecture with four layers and five ports. The approach presented in this paper allows for rapid iteration of computational and storage architectures, as well as testing of iterative storage scheduling strategies, in problems characterized by complex memory access behaviors in group convolution feature communication.

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Publication Details

Published
2024-10-25
DOI
https://doi.org/10.1109/icicm63644.2024.10814568
Primary Topic
Advanced Computing and Algorithms
Type
article
Field-Weighted Citation Impact
0.00

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article

Research on Storage Network Architecture Simulator for Group Convolution Feature Communication

Liang Yang, Junlin Hu, Kou Wang, Peng Wang et al.
Advanced Computing and Algorithms
article

Research on Storage Network Architecture Simulator for Group Convolution Feature Communication

Liang Yang, Junlin Hu, Kou Wang, Peng Wang, Dian Tian, Ningmei Yu
article en

Abstract

In group convolution, feature communication exhibits complex behaviors, leading to memory access becoming one of the factors limiting performance. For this issue, our team has proposed an on-chip storage network with adaptive bandwidth for centralized distributed storage. To verify the effectiveness of the storage network architecture and achieve rapid iteration towards the optimal architecture, this paper constructs behavioral models for group convolution computation units and storage networks based on SystemC and TLM, enabling rapid adjustment of the architecture and its models through parameters. Firstly, by analyzing the computational behavior of group convolution, we abstracted the basic behavioral model of the computation unit. Through this foundational model, complex computational behavior models for group convolution feature communication can be constructed. Secondly, we constructed models for the structures within the storage network, including routers, nodes, storage units, and bus bridges. Furthermore, an AXI interconnect model was built to facilitate data transfer between the memory access behavior model of group convolution and the storage network model. Through the storage network architecture simulator, read and write frequencies of network buses and nodes, as well as the storage utilization rates of each accessed network node, can be obtained to evaluate the performance of current architectural parameters and make appropriate adjustments to the architecture. The validity of the simulator in this paper was effectively verified through the simulation of 3×3 group convolution computation and a storage network architecture with four layers and five ports. The approach presented in this paper allows for rapid iteration of computational and storage architectures, as well as testing of iterative storage scheduling strategies, in problems characterized by complex memory access behaviors in group convolution feature communication.

Xi'an University of Technology (CN)
National Natural Science Foundation of China
Openalex Percentile: Top 57%
Advanced Computing and Algorithms
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