32Gb/s Low-Power NRZ Signal Serdes Receiver

In this paper, a SerDes receiver for receiving 32Gb/s non-return-to-zero (NRZ) signals is designed with a half-rate structure to reduce the power consumption of the circuit, and the equalisation scheme is a continuous-time linear equaliser (CTLE) and a 2-tap decision feedback equaliser (DFE) equalisation. In order to extend the high-frequency bandwidth and increase the high-frequency gain, a CTLE with Gm-TIA structure is designed; in order to reduce the power consumption, an improved StrongARM comparator and a TSPC-type D flip-flop (DFF) are designed. Using 28nm CMOS process, under 1.05/1.2V supply voltage, the post-simulation results show that: at Nyquist 16GHz frequency, the CTLE can compensate 17.42dB channel attenuation; the variable gain amplifier (VGA) can improve 12.82dB low-frequency gain, and the eye-width after DFE equalisation is O.77UI, and the eye-height is 385mV; the overall power consumption at the receiver side is 20.25mW, energy efficiency is 0.63pJ/bit, and the area of the layout core is 0.096mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. The proposed circuit is suitable for use in high speed serial interface and communication applications.