PTWT: A reduction technique of page table walking

Recently, designing multicore processor has been evolving and getting complicated. In the multicore processor system, each core has its own cache memory. It is necessary to manage coherence of cache memories to prevent contradiction between them.Translation Lookaside Buffer (TLB) in each core caches results of translation between virtual page and physical page. In the same way as the cache memory, it is required to manage coherence of TLB. The method to keep its coherence is called TLB shootdown that still relies on software in some cases nowadays. Software based TLB shootdown causes InterProcessor Interrupt (IPI) to invalidate remote core’s TLB entries. However, this method requires many cycles, which may lead to performance degradation. Therefore, some methods for hardware based TLB shootdown that invalidates TLB entries automatically are proposed. Those methods require several times of page table walking after invalidating entries.This paper proposes a new hardware module, Page Table Walk Tracer (PTWT), for reducing the number of page table walking. PTWT traces physical page numbers of page table entries that Page Table Walker (PTW) walked on. TLB entries can be automatically updated when the page tables are modified.We evaluated the reduction rate of the number of page table walking with 2 to 16 cores. The results show that there is possibility that PTWT can reduce around 8.09% to 37.3% of the number of page table walking.