A Low-Power ADC for CIM with Non-Linear Quantisation, Max Pooling, and Configurable-Threshold ReLU

For energy-efficient compute-in-memory (CIM) macros, peripheral circuits such as analog-to-digital converters (ADCs) consume the majority of power. Traditional ADCs often struggle to balance performance and power consumption effectively. This paper proposes a novel low-power ADC specifically designed for CIM applications, which integrates a configurable-threshold rectified linear unit (ReLU) function and max pooling function. Compared to the traditional ADC, the proposed ADC reduces conversions by over 80% without additional analog circuitry. Furthermore, the proposed ADC optimizes the quantization curve with an average switching power consumption of 37.8 CVref2 while maintaining network recognition accuracy. The proposed ADC is simulated using a 55-nm CMOS process with a supply voltage of 1.2 V. At a sampling frequency of 2 MHz and across the full input range, the analog power consumption is 1.6 µW. Through ADC modeling and algorithmic simulations, the classification of the CIFAR-10 dataset using the VGG16 network achieved an accuracy of 92.87%.