Anomaly Detection in Dynamic Power Events Using Data Fusion for Chip Design

This paper describes a methodology to detect anomalies in estimated dynamic power series reported by elec-tronic design automation (EDA) tools during very-large-scale integration (VLSI) semiconductor chip design. EDA software is commonly used to predict the expected behaviour of a chip prior to its manufacturing. However, the extremely complex nature of modern chip design and various simulation environment circum-stances may lead to false fluctuation (anomalies) in reported dynamic power series values, resulting in the over-allocation of resources to handle these suspected power variations. The challenge in identifying these anomalies arises from numerous testbench and design particularities, clock model jitters and a lack of an established automated process of incorporating prior data into the decision process. Given that the power fluctuation on the chip is attributed to design activities (data burst, activation of clocks, among many others), an anomaly identification approach utilizing a combination of machine learning and data fusion is proposed and compared to several other approaches. The performance of the proposed methods is evaluated using a simulated dataset consisting of different power patterns exercised over system-on-chips (SoC) design and reported with the EDA tool, post-processed by our suggested algorithm.