FPGA Implementation of a Concatenated KP4 and Hamming Code for Forward Error Correction
We implemented concatenated KP4-Hamming codes on an FPGA. The different convolutional interleaver structures are proposed and demonstrated. The results show that the best structure can achieved a BER of 3.27e-16 at a SNR of 8.9.
Authors
- Feng Tian (ORCID: https://orcid.org/0000-0001-7888-0587)
- Ze Dong (ORCID: https://orcid.org/0000-0001-5773-9461)
- Yang Tian (ORCID: https://orcid.org/0000-0003-1970-0413)
- Chuanji Yan (ORCID: https://orcid.org/0009-0002-1620-6751)
- Yutian Li (ORCID: https://orcid.org/0000-0003-1810-3000)
- Qi Zhang (ORCID: https://orcid.org/0000-0002-1511-7485)
Institutions
- Beijing Institute of Technology (CN)
- Beijing University of Posts and Telecommunications (CN)
Publication Details
- Published
- 2024-11-02
- DOI
- https://doi.org/10.1109/acp/ipoc63121.2024.10809720
- Citations
- 1
- Primary Topic
- Embedded Systems Design Techniques
- Type
- article
- Field-Weighted Citation Impact
- 0.49