An Enhanced Bandwidth and Low-Distortion Two-Stage Cascode Amplifier Based on 22-nm CMOS Process

This paper introduces an enhanced operational amplifier design, which achieves a significant bandwidth expansion of approximately 15% through an innovative application of the gm/Id methodology. The design refines the traditional folded casco de structure, integrating a modified input stage with a symmetrical PMOS input transistor to reduce circuit mismatch. Employing TSMC's 18rf process library, the design and simulation were executed within the Cadence platform. The resulting operational amplifier is capable of operating over a wide temperature range from −25°C to 125°C, consistently delivering an open-loop gain exceeding 80 dB, a phase margin beyond 60 degrees, a unit gain bandwidth over 80 MHz, a common mode rejection ratio above 60 dB, a power supply rejection ratio in excess of 80 dB, and an output voltage swing that closely approaches the positive and negative supply rails.