Design of High Data Rate Demodulator

With the rapid development of information and communication technology, the demand for communication rate is getting higher and higher. Today's communication system has become more and more difficult to meet the growing demand for communication rate, high data rate digital demodulator research has increasingly become a hot spot. In order to break through the limitations of the chip clock frequency, parallelization of the demodulator is urgent. This paper conducts research on this and proposes a parallel high data rate demodulator scheme. We focus on parallel matched filtering, parallel timing synchronization, parallel equalization, and parallel carrier synchronization algorithms and implementations, taking into account both resource saving and rate enhancement, and finally complete the simulation to verify its correctness.