A case for edge video processing with FPGA SoC: reversi board detection using Hough transform

There has been increasing needs for image and video processing at edge devices, such as low-end FPGA System-onChips (SoCs). In this paper, we present an accelerator of a reversi board detection algorithm for a Zynq-7000 SoC, to investigate advantages and limitations of edge video processing with FPGA SoC. The accelerator is developed using the AMD Vitis vision library and its pipeline includes twelve OpenCV functions. Thanks to high level synthesis, hardware generation itself is quite simple. However, a part of the algorithm has to be modified, because not all of the OpenCV functions are suitable for hardware implementation and thus supported by the library. In our case, contour detection was replaced with Hough transform. According to our evaluation, the board detection became 16.1 times and 9.4 times faster than the software implementations of the original and modified algorithms, respectively. The accelerator consumed 23%–54% of logic elements in the XC7Z020 device — 28,635 LUTs, 38,442 flip-flops, 50 DSP blocks, and 47 RAM blocks.