A Configurable Real-Time Self-Test and Repair Engine for Improving the Reliability and Functional Safety of RAM Arrays

Hard and soft errors in embedded memories have become a serious reliability issue in IoT, industrial, automotive, and other devices with stringent requirements for operating environments and reliability. A configurable self-test and repair engine is proposed to detect and repair hard errors and correct soft errors in RAM arrays on-the-fly. This scheme effectively utilizes SRAM access intervals to achieve real-time self-test and repair with configurable self-test mode, address range, and repair depth. Estimated based on the existing failure model, this scheme significantly reduces the failure rate of RAM arrays with good practicability and small hardware overhead. Evaluated with TSMC's 40nm standard CMOS technology, the implementation with 8-address repair depth for (16384×39)-bit RAM array has a lightweight feature of 4640.261 µm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>, which is only 1.68% of the RAM array area. In the case study on the FPGA platform with an embedded RISC- V core, the results show that the proposed engine causes a certain amount of increase in overhead, but almost no loss in system frequency and SRAM access efficiency.