A Lightweight, Real-Time Die-to-Die Interface Protocol and Associated Adapter

In the reusable chiplet-based SoC design, efficient cross-die data transfer with standard die-to-die (D2D) interfaces requires the utilization of D2D adapters for conversion between on-chip bus and D2D physical interface as well as corresponding protocols. However, few designs satisfy the demands for low-cost, low-power, and high real-time. This paper introduces a lightweight, real-time chiplet interface protocol and its D2D adapter circuits for edge sensing applications. The D2D adapter supports multiplexing of AHB, APB and custom message on-chip protocols and differentiated treatment of them. To meet high real-time requirement, the design assigns fixed priorities and transaction types to different on-chip buses, while using Data Bus Inversion for low-power encoding. This design has been verified to achieve a latency of 7.48 ns and a power consumption of 3.096 mW, outperforming similar designs previously proposed.

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Publication Details

Published
2024-10-25
DOI
https://doi.org/10.1109/icicm63644.2024.10814383
Primary Topic
Embedded Systems Design Techniques
Type
article
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article

A Lightweight, Real-Time Die-to-Die Interface Protocol and Associated Adapter

Sihai Qiu, Xiangyu Li, Yafei Liu, Wenyao Chen
Embedded Systems Design Techniques
article

A Lightweight, Real-Time Die-to-Die Interface Protocol and Associated Adapter

Sihai Qiu, Xiangyu Li, Yafei Liu, Wenyao Chen
article en

Abstract

In the reusable chiplet-based SoC design, efficient cross-die data transfer with standard die-to-die (D2D) interfaces requires the utilization of D2D adapters for conversion between on-chip bus and D2D physical interface as well as corresponding protocols. However, few designs satisfy the demands for low-cost, low-power, and high real-time. This paper introduces a lightweight, real-time chiplet interface protocol and its D2D adapter circuits for edge sensing applications. The D2D adapter supports multiplexing of AHB, APB and custom message on-chip protocols and differentiated treatment of them. To meet high real-time requirement, the design assigns fixed priorities and transaction types to different on-chip buses, while using Data Bus Inversion for low-power encoding. This design has been verified to achieve a latency of 7.48 ns and a power consumption of 3.096 mW, outperforming similar designs previously proposed.

Shanghai Jiao Tong University (CN), Beijing Microelectronics Technology Institute (CN), Tsinghua University (CN)
Openalex Percentile: Top 74%
Embedded Systems Design Techniques
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A Lightweight, Real-Time Die-to-Die Interface Protocol and Associated Adapter — Sihai Qiu, Xiangyu Li, et al. · (2024) | TGRS Research Map | TGRS