The MBIST Implementation of SoC Chip

With the increasing proportion of memory on SoC (System on Chip) chips, Memory Built-in Self Test (MBIST) has become a crucial component of Design for Testability (DFT) in SoC chip design. In this paper, MBIST design is based on a SoC chip in SMIC40nm process, which reuses the JTAG(Joint Test Action Group) interface and PLL(Phase-Locked Loop) on the SoC chip. The MBIST design can complete the at-speed test of all the SRAMs in the SoC chip design, which is implemented following the flow of Tessent Shell MemoryBIST. Through MBIST simulation verification and wafer test after chip fabrication, the effectiveness of MBIST circuit in screening the SoC chip's memory is demonstrated, leading to improved efficiency in chip application test.