A Novel Design of Additional Doping in Source/Drain Extension Region towards OFF-state Current Suppression in GAA-NSFETs

Gate-all-around field effect transistor (GAAFET) provides excellent gate controllability, which effectively suppresses short-channel effect (SCE). Therefore, GAAFET makes it highly promising for sub-3nm node. However, the OFF-state current resulted from the dramatically change of doping concentration at the boundaries between source/drain extension region and channel region is still a critical challenge to be solved. In this study, a novel approach involving additional doping in source/drain extension region (ADER) is proposed to suppress OFF-state leakage current, and a comparative analysis among junctionless GAAFET (JLFET) and junctionless accumulation mode GAAFET (JAMFET) is conducted. Notably, the proposed device structure avoids introducing any extra lithography process. Furthermore, the impact of structural parameters on OFF-state and ON-state current of above is investigated. In conclusion, this research presents an effective method of p-type doping in extension region to enhance device performances without significantly increasing process complexity and costs.