Comparative Study on the SRAMs Based on III-V Homojunction and Heterojunction TFETs

Although Tunnel Field-Effect Transistors (TFETs) are acknowledged for energy-efficient devices, their low on-state current significantly constrains their development. In contrast to conventional TFETs, III-V heterojunction TFETs demonstrate steeper switching characteristics and higher on-state currents. This paper employs a semi-empirical Verilog-A compact model to conduct a comparative analysis of the performance of 8T SRAM cells utilizing GaAsSb/InGaAs heterojunction and InGaAs homojunction TFETs through Spectre simulation. The results reveal that, compared to the homojunction configuration, SRAM cells based on heterojunction TFETs exhibit a marked decrease in read/write delay but an increase in read/write power consumption, with no significant change in noise margin. This suggests a trade-off between speed and power performance metrics in the design of SRAM cells utilizing heterojunction TFETs. Furthermore, the variability of SRAM based on these two types of TFETs is analyzed, indicating that SRAM utilizing the heterojunction structure is more susceptible to process variations.