A 16-bit Low-Power DAC Based on Hybrid Structure
The design of high-precision digital-to-analog converter (DAC) is crucial for applications requiring accurate signal conversion in various high-performance systems. This paper presents the design of a high-precision DAC circuit with a 16-bit resolution, based on a hybrid structure. The structure uses a “2+6+8” segmented thermometer code, incorporating both a voltage-type R-2R ladder and a current injection structure. The 8-bit LSB control the position of the current sources connected to the resistor string, generating different weighted voltages through resistor division. Additionally, a high-gain, wide-output swing operational amplifier buffer is designed to amplify the output voltage while maintaining low current consumption. This design is able to derive high resolution and high performance, in terms of differential nonlinearity (DNL) and integral nonlinearity (INL), and less power consumption comparing with conventional DACs. Simulation results validate clearly the effectiveness of this design. At a sampling frequency of 200 kHz, the output signal's signal-to-noise and distortion ratio (SNDR) is 91.1 dB, and spurious-free dynamic range (SFDR) is 105.43 dB. And the total average power consumption is only 6.3 mW.
Authors
- Hanbo Jia (ORCID: https://orcid.org/0000-0002-8719-5757)
- Kai Sun (ORCID: https://orcid.org/0000-0002-0343-6032)
- Qi Sun (ORCID: https://orcid.org/0000-0002-7092-0705)
- Xuan Guo (ORCID: https://orcid.org/0000-0001-8052-6165)
- Danyu Wu
- Heping Ma (ORCID: https://orcid.org/0000-0002-7551-2639)
Institutions
- Chinese Academy of Sciences (CN)
- Institute of Microelectronics (CN)
- Institute of Semiconductors (CN)
- University of Chinese Academy of Sciences (CN)
Publication Details
- Published
- 2024-10-25
- DOI
- https://doi.org/10.1109/icicm63644.2024.10814145
- Primary Topic
- Advanced Memory and Neural Computing
- Type
- article
- Field-Weighted Citation Impact
- 0.00