A DC-50 GHz 6-bit Digital-Step Attenuator with 31.5 dB Tuning Range in 28-nm Bulk CMOS

This letter presents a DC-50 GHz 6-bit digital-step attenuator (DSA). By using capacitive compensation technology and phase compensation structure, the amplitude error and phase variation is reduced. The attenuator is fabricated using TSMC 28-nm bulk CMOS process, with a core area of 0.063 mm2, The measured insertion loss of the attenuator at working frequency of DC to 50 GHz is 2.37 - 11 dB. The total attenuation range is 31.5 dB with a step of 0.5 dB. Within the 31.5 dB tuning range, the attenuator has a maximum phase variation of 12° and an RMS phase variation of 6.4°, with a maximum amplitude error of 1.2 dB.