A Low-Power 50 Gb/s PAM4 High-Speed SerDes Transmitter

For high-speed serial interface transmitter applications, this paper presents the design of a 50 Gb/s low-power 3-tap/4-tap configurable forward feedback equalization (FFE) four-level pulse amplitude modulation (PAM4) high-speed serial interface (SerDes) transmitter based on UMC 28 nm CMOS technology. The design adopts a half-rate PAM4 transmitter architecture. The design ingeniously replaces the traditional power-hungry current-mode logic (CML) structure with C<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>MOS latches and selectors, facilitating data delay and rate synthesis before the data reaches the combined driver. This approach significantly reduces the transmitter's power consumption. The configurable 3-tap/4-tap FFE fine-tunes the equalization coefficients using a digital-to-analog converter (DAC), ensuring optimal signal integrity. Moreover, the output driver utilizes inductive peaking technology to extend the bandwidth, crucial for maintaining high-speed data transmission. Simulation results show that at 1.05 V supply voltage, the differential output eye height for 50 Gb/s PAM4 output is 86 mV with an eye width of 20.8 ps (0.52 UI) and the power consumption of 71.58 mW (energy efficiency is 1.4316 pJ/bit) when the 3-tap FFE is in use. The differential output eye height is 90 mV with an eye width of 20.8 ps (0.52 UI) and the power consumption of 72.99 mW (energy efficiency is 1.4598 pJ/bit) when the 4-tap FFE is in use. The overall layout area of the transmitter is 0.036 mm”.