Review of TSVs Testing Between Chiplets

As semiconductor technology advances, traditional 2D integrated circuits can no longer meet demands, leading to the rise of Chiplet heterogeneous integration. Through-Silicon Via (TSV) technology enhances data transfer speed, bandwidth, and integration density while reducing power consumption and package size through vertical interconnections. This paper introduces pre-bond and post-bond TSV testing methods, including on-chip and probe-based techniques, and highlights the TSV Built-In Self-Test (BIST) repair mechanism for identifying and repairing defects. These advancements address TSV testing complexity challenges, providing insights for optimizing 3D stacked integrated circuits.