Research of Key Technologies for 12-bit SAR ADC

With the rapid development of modern intelligent industries such as wireless communication, the Internet of Things, medical devices, and autonomous driving technology, the performance requirements for smart sensors are increasingly high for analog-to-digital converters. This article conducts a survey of a large number of SAR ADCs, summarizes the design methods of various key circuit modules, and designs a 12-bit, 25MS/s sampling rate fully differential input SAR ADC. This paper presents a 12-bit 25MS/s successive approximation register analog-to-digital converter (SAR ADC) based on the extended C-2C capacitor array and FIA comparator, the structure not only speeds up the level conversion rate, reduces power consumption, but also reduces the mismatch of the bridging capacitor. The SAR ADC is realized in a 55nm CMOS process. In the supply voltage 1.2V, sampling rate 25MS/s, input signal frequency close to the Nyquist frequency, the SAR ADC pre-simulation results show that its ENOB is 11.89bits, SNDR is 73.34dB, SFDR is 83.42dBc. Post-simulation results show that the ENOB of SAR ADC is 10.73bits, SNDR is 73.34dB, SFDR is 83.42dBc, SNDR is 66.36dB, SFDR is 82.16dBc, power consumption is 417.59µW, FoMW is 9.83fJ/conv-step, FoMS is 171.12dB.