FPGA Implementation of Low Complexity Timing Recovery with High SCO Tolerance for IM/DD Optical Data Links
We implement a low-complexity timing recovery on FPGA platform, leveraging an advanced data buffer and timing error detector. Its stability and high SCO tolerance are verified through real-time experiments with 29.4912 Gbps PAM4 signals.
Authors
- Chen Cheng (ORCID: https://orcid.org/0009-0000-6308-6946)
- Weisheng Hu (ORCID: https://orcid.org/0000-0002-6168-2688)
- Tonghui Ji (ORCID: https://orcid.org/0000-0003-3453-0248)
- Yuting Xu (ORCID: https://orcid.org/0000-0001-7640-4018)
- Zhaopeng Xu (ORCID: https://orcid.org/0000-0001-6476-9001)
- Bang Yang (ORCID: https://orcid.org/0000-0002-0029-9511)
- Jinlong Wei (ORCID: https://orcid.org/0000-0001-7714-5003)
- Jianwei Tang (ORCID: https://orcid.org/0009-0007-6506-0046)
- Jianyu Wang (ORCID: https://orcid.org/0000-0002-3926-7234)
- Zhongliang Sun (ORCID: https://orcid.org/0000-0002-5559-4892)
- Yaguang Hao
- Xiaofeng Cui (ORCID: https://orcid.org/0000-0003-2761-3934)
- Cancan Chen (ORCID: https://orcid.org/0000-0001-9743-0581)
- Junpeng Liang (ORCID: https://orcid.org/0000-0002-0594-9579)
Institutions
- Harbin Institute of Technology (CN)
- Peng Cheng Laboratory (CN)
Publication Details
- Published
- 2024-11-02
- DOI
- https://doi.org/10.1109/acp/ipoc63121.2024.10809547
- Citations
- 2
- Primary Topic
- Advanced Optical Network Technologies
- Type
- article
- Field-Weighted Citation Impact
- 0.42
Funders
- Science, Technology and Innovation Commission of Shenzhen Municipality
- National Key Research and Development Program of China