Design of a Capacitance Measurement Circuit and System with Parasitic Capacitance Elimination
In the application system of capacitive sensors, the capacitance values of these sensors are generally small. It is crucial to remove the influence of parasitic capacitance. In order to achieve this goal, this paper introduces a capacitance time conversion measurement circuit and system that remove parasitic capacitance. The capacitance value is indirectly measured by the time when the capacitor is charged. The entire measurement circuit includes an MCU core, I/O with pull-up resistor, TDC (Time to Digital Converter) to count the charging time, MCU commands to switch the measurement mode, and calculates the measurement results to eliminate the influence of parasitic capacitance. The measurement results presented in the article show that parasitic capacitance can almost completely be eliminated. This method can be applied to various capacitance measurement scenarios.
Authors
- Yaoming Lv
- Hong Yang (ORCID: https://orcid.org/0000-0003-2860-5901)
- Feng Zou (ORCID: https://orcid.org/0000-0002-8749-8088)
- Yuhua Cheng (ORCID: https://orcid.org/0009-0007-1973-3481)
Institutions
- Peking University (CN)
- Institute of Microelectronics (CN)
Publication Details
- Published
- 2024-10-25
- DOI
- https://doi.org/10.1109/icicm63644.2024.10814333
- Primary Topic
- Sensor Technology and Measurement Systems
- Type
- article
- Field-Weighted Citation Impact
- 0.00