A 350MHz, 10bit, 500-fs Resolution Asynchronous Pipelined-SAR Time-to-Digital Converter

High-speed, high-resolution and high-linearity time-to-digital converters (TDCs) are the key components in digital phase-locked-loops(DPLLs) and time-domain analog-to-digital converters(ADCs). The time amplifier (TA) based TDCs have achieved high resolution. However, the variation of the TA gain reduces linearity, which need additional calibration circuits. This paper proposes a high-resolution and high-speed asynchronous pipelined-successive approximation register(SAR) time-to-digital converter (TDC). The one-bit delay stage of the proposed TDC is realized by a constant slope digital-to-time converter (DTC) which achieves high linearity and high resolution. To improve the conversion rate of the SAR TDC, an asynchronous pipelined operation strategy is proposed. Moreover, a pulse width recovery circuit is proposed to maintain the linearity of the DTC at a high conversion rate. Simulations show that the TDC designed in 40 nm CMOS achieves 10-bit, 500 fs of time resolution, 0.8 LSB DNL and 1.6 LSB INL at 350 MHz sampling frequency consuming 14.72 mW power, which corresponds to 106.74 fJ/Conv. FoM.