A Novel Compensation Circuit for Enhanced Linearity and Accuracy in In-Memory Computing

In-memory computing (IMC) based on non-volatile memory faces several challenges, such as IR Drop effects and inter-channel gain errors caused by non-ideal factors in the IMC's readout system. This paper proposes a novel compensation circuit incorporating differential port clamping and offset storage to address these issues. The designed circuit ensures consistent and linear device output current. In a 55-nm CMOS process, PVT and Monte Carlo simulation results demonstrate a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$96 \%$</tex> reduction in current non-linearity within a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0-40 \upmu ~\mathrm{A}$</tex> range of device output current and a 99.9 % reduction in inter-channel gain error (3б), indicating significant improvement over conventional methods.