A Low-Noise Energy-Efficient Double-Tail Dynamic Latch Comparator

As the primary source of power consumption and noise in ADCs, the comparator's performance is critical to the ADC performance. This paper proposes a low-noise energy-efficient double-tail dynamic latch comparator. By analyzing the traditional double-tail dynamic latch comparator structure and its noise source, this work proposes improvements that balance noise and power consumption. The pre-amplification stage is enhanced with cross-coupled pairs to boost amplification gain, the latch stage current transistors are switched to NMOS for lower power consumption, and capacitors are added to the first-stage output to minimize equivalent input noise. The prototype is designed in UMC 110nm process, and the layout area of the proposed comparator is 8 µm × 70.4 µm. At a power supply voltage of 3.3V, operating frequency of 40MHz, and a comparison step size of 244µ V, the comparator achieves an input noise of 207 µ Vrms and a FoM of 8.3349 nJ·(µV)2.