A 10-bit 100MS/s SAR ADC with Optimized Power Efficiency in 28nm CMOS Technology

This paper presents a 10-bit 100 MS/s Successive Approximation Register Analog-to-Digital Converter (SAR ADC), fabricated in a 28nm CMOS process, that prioritizes low power consumption and high power efficiency. Employing techniques such as a double-bootstrapped switch, a dynamic comparator combined with a three-stage preamplifier structure, and a novel dynamic logic cell circuit. These known techniques are combined in a novel way to achieve specific performance goals such as low power consumption and optimized power efficiency. A superior balance between power consumption and performance has been found. At the same time, the challenges associated with small process sizes, such as increased leakage current and short-channel effects, are effectively improved in the 28nm CMOS process. Simulation results demonstrate that the designed SAR ADC meets design requirements with an Effective Number Of Bits (ENOB) of 8.35 bits, a Signal-to-Noise Ratio (SNDR) of 52.05 dB, and a Spurious-Free Dynamic Range (SFDR) of 69.48 dBc under a supply voltage of 0.9 V. It exhibits excellent performance and power efficiency, with an average power consumption of only 487 µW. This design achieves a balanced performance in signal acquisition and processing with moderate accuracy and speed, while emphasizing low power consumption, providing a solution that optimizes efficiency and performance for a broad range of technical applications.