A 3-GS/s 12-Bit Time-Interleaved Wideband Pipeline ADC Using Sample-and-Hold Amplifiers

A 3-GS/s 12-bit two-channel time-interleaved analog-to-digital converter (ADC) is described in this paper. The ADC employs two sample-and-holding amplifiers (SHAs) at the front end, which drive two pipeline sub-ADCs to interleave samples to achieve a 3 GS/s sampling rate. The SHA with 1.5x gain can relax the linearity requirement of the input buffer and ensure sufficient input amplitude for the subsequent sub-ADC. The front-end bandwidth of the ADC presented in this paper reaches up to 6 GHz. Fabricated in a 28-nm CMOS process, the prototype ADC achieves an outstanding SNDR of 53.71 dB at 3 GS/s with a 1.227 GHz input. The ADC core area is 1.66 mm-, including the digital part, the power consumption is 1408 mW.