A Bandwidth-Adaptive On-Chip Storage Network Architecture

A scalable bandwidth-adaptive on-chip storage network architecture is proposed to address the severe data conflict and low bus parallelism in existing multi-level storage, Crossbar, and NoC architectures in edge accelerated computing. This architecture combines the advantages of centralized and distributed memory, allowing the memory hierarchy to be flexibly adapted based on current computational needs and memory access patterns to better accommodate multi-core processors and parallel computing requirements. This paper designs the result visualization method to visualize the stress of storing each node and bus. Furthermore, the full path test incentive is intended for the secondary sharing policy and router. The feasibility of this paper's architecture is verified through VCS simulation and visualization analysis.