A Single-Channel 2-GS/s 8-bit Two-Step SAR ADC in 28nm CMOS
This paper presents a single-channel 8-bit 2 GS/s two-step successive approximation register (SAR) analog-to-digital converter (ADC). Combined with the passive residue transfer and comparators alternation technology, the proposed SAR ADC is currently one of the fastest single-channel 8-bit SAR ADCs, and its performance is superior to time-interleaved SAR ADCs at the same resolution and sampling rate. The proposed ADC in 28-nm CMOS consumes 6.91 mW at 2 GS/s with a 1V supply. It achieves a Nyquist SNDR of 45.6 dB and results in an FoM of 22.2 fJ/conv.-step.
Authors
- Wei Han (ORCID: https://orcid.org/0000-0003-2177-004X)
- Tiehu Li (ORCID: https://orcid.org/0000-0001-6861-4269)
- Jia-Yan Tang
- Jiayi Gui (ORCID: https://orcid.org/0000-0003-2371-4690)
- Shenglei Zhao (ORCID: https://orcid.org/0000-0002-1406-1088)
- Jianwei Liu (ORCID: https://orcid.org/0000-0002-9357-1202)
- Xin Fu (ORCID: https://orcid.org/0000-0002-6279-4104)
Institutions
- Xidian University (CN)
- Chongqing University of Technology (CN)
Publication Details
- Published
- 2024-10-25
- DOI
- https://doi.org/10.1109/icicm63644.2024.10814399
- Primary Topic
- Analog and Mixed-Signal Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 0.00