A 12bit/100kHz Two-Step Single-Slope ADC for SWIR Image Sensor Based on CMOS 180nm Process

This paper presents a 12bit/100kHz column-level two-step single-slope ADC (TS-SS ADC) designed for SWIR image sensor to achieve the area efficiency, high sensitivity and rapid response speed. The proposed ADC employs a dynamic adjustable reference voltage compensation and a four-terminal input comparator to enhance resolution and reduce charge leakage. The two-step architecture divides the quantization process into coarse and fine stages, significantly improving speed and precision. A prototype ADC was implemented in a 180nm CMOS technology, which achieves an SNDR of 72.7 dB and an SFDR of 80.7 dB under a 3.3V supply at a sampling frequency of 100 kS/s. The input voltage range is 1.7 V, with an ENOB of 11.78 bits. The ADC core occupies an active area of 0. 7226mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. The proposed ADC demonstrates superior performance for advanced SWIR imaging applications.