A 6-Bit Attenuator Design with High Attenuation Accuracy and Low Additional Phase Shift

In this paper, a 6-bit attenuator is designed based on GaAs 0.15 um pHEMT process, in which different attenuation structures are cascaded in the optimal order, and inductive and capacitive phase compensation structures are added on the basis of the traditional attenuator design in order to obtain better phase shift and attenuation error, and the maximum attenuation range of 31.5 dB and the attenuation step is 0.5 dB are finally realized, and the simulation results show that the designed attenuator has the following performance. Simulation results show that the designed attenuator has an input/output return loss of less than - 19 dB, an insertion loss of less than 1.5 dB, an attenuation error of less than 0.25 dB, and an additional phase shift of ±1 in DC-4 GHz, and meanwhile, the area of the designed chip is 1.8×0.9×0.1 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup>.