A High-Speed Low-current-Mismatch PFD+CP Circuit for 11.3G CPPLL Application

Combination circuit of PFD and CP was designed using 65nm CMOS technology to achieve low jitter and high frequency. Some techniques, such as TSPC, cascade structure and gain enhancement technology, can be employed into PFD and CP to suppress unfavorable factors, such as charge sharing, current mismatch, leakage current, etc. Simulation results show that the variation of voltage is almost linear and the basic invariable control voltage in the transient process, showing that it cannot also introduce the significant frequency jitter. CP current matching accuracy is about 0.047% in the range of 0.35V~0.8V and the maximum total leakage current in the range of 0V~l.2V is 23.3pA, which can effectively be reduced to improve jitter performance.