Analysis and Design of High Efficiency CMOS RF Class-D Power Amplifier

The practical power-added-efficiency (PAE) of class-D RF power amplifier (PA) deviates from the theoretical value 100% greatly because of some inevitable non-ideal effects. This paper proposes three design considerations to improve the performance of class-D RF PA. Based on those design considerations, two pieces of class-D RF PA, powered by 1.8V and 3.3V supply respectively, have been implemented by standard CMOS 0.18um process. With 800MHz stimulus, measurement results show that the PAE and output power reach 42% and 10.5dBm for 1.8V supply part, 38% and 15.4dBm for 3.3V supply part, which demonstrates the practicability of the introduced design considerations.