Hardware Design and Security Analysis for cSHAKE256 in PQC SIAKE

With the development of quantum computing, traditional public-key encryption algorithms are facing unprecedented threats, and it is urgent to develop cryptographic algorithms that can resist the attack from quantum computing. SIAKE is a Supersingular Isogeny based authenticated key exchange algorithm. In SIAKE, cSHAKE256 is a key step in 2-Key PKE based on homology calculations. cSHAKE256 is an extensible hash function in the SHA-3 family that further enhances flexibility and security with Customization strings and function names. This paper presents a hardware structure of cSHAKE256 suitable for SIAKE. First, the domain separation module specific to cSHAKE256 is designed. Secondly, the iteration function is optimized to achieve 2 iterations in one cycle. Finally, the 3-stage pipeline structure is adopted in Keccak function algorithm and the wheel constant is simplified, which can greatly improve the throughput and save some resources. The design is verified on FPGA Xilinx Virtex-7, the results show that the designed cSHAKE256 hardware unit has a maximum operating frequency of 217MHz. Finally, the hardware structure of cSHAKE256 is analyzed for side channel security. The design and implementation of cSHAKE256 is proven to be directly applicable to SIAKE, providing it with the necessary security and randomness.