Research on Successive Approximation Analog-to-Digital Converter Circuit for Readout Circuit

The imaging quality in an array detector is directly impacted by the analog-to-digital converter (ADC) unit: as detection arrays progress towards higher density, precision, and longer distances, the demands for ADC circuit accuracy and footprint become increasingly stringent. This study is centered on investigating and developing an Analog-to-Digital Converter (ADC) circuit tailored for the quantization of analog signals. Specific research areas include: (1) The development of a 12-bit Successive Approximation Register (SAR) ADC. This circuit employs bootstrap sampling switches, a timing sequence based on VCM-split capacitor array top-plate sampling, and utilizes multi-stage bridged capacitor arrays to significantly reduce capacitor footprint. (2) Incorporating bandgap and Low Dropout Regulator (LDO) circuits, the design of bias circuits for the system involves the utilization of a comparator reset clock to effectively govern the initiation of the bias circuit., thereby reducing circuit power consumption during comparator reset periods.