Hardware Design and Security Analysis for SHA-256 in PQC Sphincs+

The development of quantum computers poses significant threats and challenges to modern cryptography, leading to the emergence of post-quantum cryptographic algorithms. Currently, the post-quantum SPHINCS+ algorithm has been listed by NIST as one of the four standardized algorithms. This paper focuses on the hardware implementation of one of the underlying algorithms for the SPHINCS+ algorithm, specifically the SHA-256 algorithm. Since all components used in the signature process are computed using the SHA-256 algorithm, there is an urgent need to design a high-throughput SHA-256 algorithm dedicated to the SPHINCS+ algorithm. This paper presents a SHA-256 algorithm design with a throughput of up to 2844-Mbps at a clock frequency of 100-MHz, utilizing the SAKURA-G FPGA as the implementation and verification platform. This paper also extracted and analyzed the power consumption of the hardware code, proposing the addition of data masking operations to make it difficult to extract critical data from power consumption curves. Through verification, the SHA-256 design presented in this paper is suitable for the postquantum SPHINCS+ algorithm.