A Configurable Computing Architecture for Split-Radix FFT

Image recovery algorithms applied to imaging systems such as lensless imaging in end devices are a high-speed edge computing process. Diffraction recovery algorithms typically include operations such as FFT/IFFT, amplitude constraint, phase constraint, and intensity operations. FFT/IFFT, as the main operation in these algorithms, is usually computed using the butterfly algorithm, which can be categorized into three main types: single-base algorithm, mixed-radix algorithm, and split-radix algorithm. To meet the hardware resource constraints of edge devices, this paper proposes a configurable computing architecture for the SRFFT algorithm by analyzing the specific butterfly unit structures. Using mode control signals, the architecture can be configured into three modes: basic butterfly unit computation, 8-point tail computation, and 2-point tail computation. By reusing the underlying floating-point computation units, the proposed architecture not only computes the FFT efficiently compared to other split-radix algorithms but also further reduces the utilization of the underlying computational resources, making it highly suitable for edge devices with limited resources.