Critical Path Optimization for Logic Netlists

It is of great concern for high performance microprocessors to optimize logic delay and improve performance in the semi-custom design flow based on commercial standard cell library. To solve this issue, the paper proposes an automated method to optimize the delay of critical path in any block. Firstly, we construct the logic cone for critical paths based on the logic netlist obtained from semi-custom design flow. Secondly, the algorithm conducts large-scale graph partitioning on the logic cone with appropriate constraints. Thirdly, using two-level optimization, we perform logic restructuring on sub graphs resulting from partitioning to get a set of new logic cells. Finally, employing a match algorithm, we pick out high-reusable restructured logic cells for full-custom circuit implementation and replace corresponding circuit structures with them in the logic netlist. The proposed algorithm picks out 5 logic cells for restructuring. Experimental results demonstrate that the approach achieves a reduction in the logic levels and logic delay can be reduced by about 10% after replacing the corresponding structures in the logic netlist. The work effectively reduces critical path delay, which has the potential to enhance the performance of microprocessors.