An Improved Cascoded Ring Amplifier Based Pipelined-SAR ADC with a Continuous Time Second Stage

This paper presents a ring amplifier based pipelined-SAR analog-to-digital converter (ADC). In advanced technology, the ring amplifier's three-stage inverter provides limited gain, so the self-biased cascoded output stage is designed to enhance the gain of the ring amplifier. In addition, a continuous time SAR is adopted to speed up the second stage, which improves the power efficiency and is not affected by the frequency of the input signal. This ADC is completed with a 28 nm CMOS process. The 12-bit ADC achieves 64.1 dB signal-to-noise-and-distortion-ratio (SNDR) at a Nyquist input, with a sampling rate of 250 MS/s and a power consumption of 0.8 mW.