A High Power Supply Rejection NMOS LDO with Dual-Loop and Charge Pump

This paper presents a high power supply rejection (PSR) NMOS low dropout regulator (LDO) with dual-loop and charge pump. A dual-loop voltage follower that is capable of providing a high PSR through an inner fast loop and a NMOS as a power transistor. The charge pump raises the supply voltage to 1.5 times the supply voltage to power the error amplifier to ensure low dropout voltage. Post-simulation results indicate an output voltage of 896 mV with merely a 304 mV voltage dropout. The post-simulated PSR is −50 dB at 10kHz and the worst PSR of −18.7 dB at 1MHz over the full band. The undershoot/overshoot is 56 mV/12.8 mV. The total static power consumption is 756 μA.