A High-Speed Dynamic Comparator Through Body-biasing and Clock Boosting

A high speed dynamic comparator is proposed in this paper. The comparator features body biasing of the differential input transistors and clock boosting charge pump to enhance the transconductances adaptively, thereby accelerating comparison speed. The comparator exhibits low offset and is suitable for high-speed 8-bit SAR-ADC applications. Compared to the conventional double-tail comparator, the proposed design achieves a nearly 50% increase in speed and a 2x reduction in power consumption. Furthermore, compared with the conventional strong-arm latch based comparator, the proposed comparator achieves a 30% increase in speed at 40 nm SMIC process.